`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: Westlake University
// Engineer: shenziyang@westlake.edu.cn
// 
// Create Date: 2021/11/24 08:48:04
// Design Name: HW5
// Module Name: tb_motor_FSM
// Project Name: hw5
// Target Devices: VCU118
// Tool Versions: vivado 2020.1
// Description: testbench for Homework 5
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module tb_motor_FSM();
    reg clk;
    reg dir;
    reg rst_n;
    wire [3:0] A;

    initial begin
        clk = 0;
        rst_n = 1;
        dir = 0;
        #10 rst_n = 0;
    end

    always begin
        #5 clk = 1; #5 clk = 0;
    end

    always begin
        #80 dir = 1; #80 dir = 0;
    end


motor_FSM inst_motor_FSM(clk,dir,rst_n,A);
endmodule
